SEGGER · Comparison of all modelsReference
Comparison of all J-Link / J-Trace models
Overview
Product overview
The Comparison of all J-Link / J-Trace models is a reference document we prepared. It compares SEGGER's 7 J-Link debug probe models and 4 J-Trace models side by side and summarizes trace support by core and the criteria for choosing between J-Link and J-Trace. It is not a product in itself.
Positive ONE Group supports you in Japanese, from product selection and quotes through to technical support during deployment, and proposes the optimal configuration for your target MCU, OS, quantity, and application.
Three things to take from these tables
① J-Link BASE and PLUS have identical hardware performance. The only difference is the software license.
② The cores supported by J-Link do not vary by model. Only three things differ: speed, connection type, and license.
③ No J-Link model supports ETM. Continuous instruction trace requires J-Trace, and this must be decided at the board-design stage.
① J-Link BASE and PLUS have identical hardware performance. The only difference is the software license.
② The cores supported by J-Link do not vary by model. Only three things differ: speed, connection type, and license.
③ No J-Link model supports ETM. Continuous instruction trace requires J-Trace, and this must be decided at the board-design stage.
Technical Details
Technical details
Connection and debug method
Connects to the target MCU's debug port (JTAG/SWD) to halt, run, and single-step the CPU core. Supports hardware breakpoints and watchpoints, reading and writing memory and registers, and programming flash memory.
Where it fits in the development flow
Used throughout embedded development: from bring-up right after power-on (checking clock and pin settings) to stepping through the application, live variable monitoring, and verifying programming before production.
IDE and tool integration
Works with the main IDEs and GDB-based debug environments. It fits easily into an existing flow, and one probe covers several MCU families — a practical advantage.
Comparison of all 7 J-Link models
Most important: BASE and PLUS have identical hardware performance. Both run at 1.0 MB/s and 15 MHz. The difference is only the licensing of software features. Choosing BASE means giving up Ozone, J-Flash, Unlimited Flash Breakpoints, and Monitor Mode. Conversely, if you want speed, choose ULTRA+ / PRO rather than PLUS (4.0 MB/s, 50 MHz).
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| Item | J-Link BASE J-LINK-BASE | J-Link PLUS J-LINK-PLUS If unsure, choose this | J-Link WiFi J-LINK-WIFI | J-Link ULTRA+ J-LINK-ULTRA | J-Link PRO J-LINK-PRO | J-Link PRO PoE J-LINK-PRO-POE | J-Link EDU Mini J-LINK-EDU-MINI |
|---|---|---|---|---|---|---|---|
| Hardware specifications (cannot be changed later) | |||||||
Host connection | USB | USB | USB / WiFi | USB | USB / Ethernet | PoE / Ethernet / USB | USB |
Download speed into RAM Actual figures depend on the target | 1.0 MB/s | 1.0 MB/s | 1.0 MB/s | 4.0 MB/s | 4.0 MB/s | 4.0 MB/s | 200 KB/s |
Target interface speed JTAG / SWD maximum | 15 MHz | 15 MHz | 15 MHz | 50 MHz | 50 MHz | 50 MHz | 4 MHz |
SPI interface speed With external SPI flash connected directly | 12 MHz | 12 MHz | 12 MHz | 50 MHz | 50 MHz | 50 MHz | 4 MHz |
SWO speed | 30 MHz | 30 MHz | 30 MHz | 100 MHz | 100 MHz | 100 MHz | 4 MHz |
VCOM baud rate Virtual COM port | 115,200 Bd | 115,200 Bd | 115,200 Bd | 10 MBd | 10 MBd | 10 MBd | Not supported |
High Speed Sampling Real-time sampling of variables | 1 kHz | 1 kHz | 1 kHz | Unlimited | Unlimited | Unlimited | 1 kHz |
Supported target voltage | 1.2〜5 V | 1.2〜5 V | 1.2〜5 V | 1.2〜5 V | 1.2〜5 V | 1.2〜5 V | 1.8 V / 3.3 V |
Target power via USB PoE only; power can be supplied from the target-side USB-A port | ✕ | ✕ | ✕ | ✕ | ✕ | ✓ | ✕ |
| Target interface | |||||||
JTAG / cJTAG | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
SWD / SWO | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Microchip ICSP PIC32 family | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
Renesas FINE RX family | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
VCOM (virtual COM) Not available with 4-wire JTAG; disabled by default | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
| Trace ★ limitation common to all J-Link models | |||||||
ETB / MTB Trace Target on-chip buffer | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Cortex ETM Trace → J-Trace required | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ |
Cortex-A PTM Trace → J-Trace required | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ |
RISC-V N-Trace BTM → J-Trace required | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ |
| Software features (licensed; can be added later) | |||||||
Flash Download | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
GDB Server | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Real-Time Transfer (RTT) | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
J-Flash Production / batch programming | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
J-Flash SPI | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
Unlimited Flash Breakpoints Unlimited breakpoints in flash | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Ozone (debugger) | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
Monitor Mode debugging BASE/OB: evaluation mode only | Evaluation only | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
RDI / RDDI | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
| Supported cores (★ no difference between J-Link models) | |||||||
Arm Cortex-M / A / R M0–M85, A5–A72, R4–R52 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Arm legacy ARM7 / 9 / 11 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Cadence Tensilica Xtensa LX6/LX7, HiFi, Fusion | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Microchip PIC32 MX / MZ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Renesas RX RX110〜RX671 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
RISC-V RV32 / RV64 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
SiLabs 8051 EFM8 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
| Commercial use | |||||||
Commercial use EDU Mini: non-commercial use only | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ |
✓ Supported ✕ Not supported Orange values = restrictions apply
Supported cores do not vary by J-Link model. BASE and PRO cover the same range of cores (EDU Mini excepted). What matters in choosing a model is speed, connection type, and software license; you do not need to worry about core support.
Comparison of all 4 J-Trace models
All J-Trace models share the same hardware performance and software features. 4.0 MB/s, TPIU 300 MHz, trace clock 150 MHz, 50 MHz. They include J-Flash, Ozone, Unlimited Flash Breakpoints, and debug functions equivalent to J-Link (so you do not need to buy a J-Link separately).
What differs is which architectures they can trace.
What differs is which architectures they can trace.
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| Item | J-Trace PRO All architectures | J-Trace PRO Cortex-A/R/M | J-Trace PRO Cortex-M | J-Trace PRO RISC-V |
|---|---|---|---|---|
| Hardware specifications (common to all models) | ||||
Host connection | USB 3.0 / Ethernet | USB 3.0 / Ethernet | USB 3.0 / Ethernet | USB 3.0 / Ethernet |
Download speed into RAM | 4.0 MB/s | 4.0 MB/s | 4.0 MB/s | 4.0 MB/s |
Maximum CPU frequency | Unlimited | Unlimited | Unlimited | Unlimited |
Maximum TPIU frequency Trace port | 300 MHz | 300 MHz | 300 MHz | 300 MHz |
Maximum trace clock | 150 MHz | 150 MHz | 150 MHz | 150 MHz |
Maximum SWO speed | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
Target interface speed | 50 MHz | 50 MHz | 50 MHz | 50 MHz |
| Trace support ★ this is where models differ | ||||
Unlimited streaming trace Live analysis (coverage / profiling) | ✓ | ✓ | ✓ | ✓ |
Buffer Trace | ✓ | ✓ | ✓ | ✓ |
Cortex-M ETM Trace | ✓ | ✓ | ✓ | ✕ |
Cortex-A ETM Trace | ✓ | ✓ | ✕ | ✕ |
Cortex-R ETM Trace | ✓ | ✓ | ✕ | ✕ |
Cortex-A PTM Trace | ✓ | ✓ | ✕ | ✕ |
RISC-V N-Trace BTM | ✓ | ✕ | ✕ | ✓ |
| Software features (common to all models) | ||||
J-Link debug functions No separate J-Link needed | ✓ | ✓ | ✓ | ✓ |
J-Flash / J-Flash SPI | ✓ | ✓ | ✓ | ✓ |
Ozone | ✓ | ✓ | ✓ | ✓ |
Unlimited Flash Breakpoints | ✓ | ✓ | ✓ | ✓ |
RTT / GDB Server / RDI | ✓ | ✓ | ✓ | ✓ |
✓ Supported ✕ Not supported
Choosing is simple. For Cortex-M only, choose Cortex-M; if Cortex-A/R is included, Cortex-A/R/M; for RISC-V, RISC-V; if several architectures are mixed or the future is uncertain, J-Trace PRO (all architectures).
J-Trace: trace support matrix by core
This matrix alone determines which J-Trace model to choose. D = debug supported (execution control, memory access); D+T = debug plus pin trace. “D only” means you can debug that core but cannot trace it.
Easy to overlook: Cortex-M0 / M0+ / M1 / SC000 are “D” only on every J-Trace. These cores have no ETM, so buying a J-Trace will not give you instruction trace. If you need trace, you must choose a Cortex-M3 or later core — this is decided at the MCU selection stage.
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| Core | J-Trace PRO | J-Trace PRO Cortex-A/R/M | J-Trace PRO Cortex-M | J-Trace PRO RISC-V |
|---|---|---|---|---|
| Arm Cortex-A | ||||
Cortex-A5 | DT | DT | ✕ | ✕ |
Cortex-A7 | DT | DT | ✕ | ✕ |
Cortex-A8 | DT | DT | ✕ | ✕ |
Cortex-A9 | DT | DT | ✕ | ✕ |
Cortex-A12 | DT | DT | ✕ | ✕ |
Cortex-A15 | DT | DT | ✕ | ✕ |
Cortex-A17 | DT | DT | ✕ | ✕ |
Cortex-A32 | DT | DT | ✕ | ✕ |
Cortex-A35 | DT | DT | ✕ | ✕ |
Cortex-A53 | DT | DT | ✕ | ✕ |
Cortex-A55 | DT | DT | ✕ | ✕ |
Cortex-A72 | DT | DT | ✕ | ✕ |
| Arm Cortex-M | ||||
Cortex-M0 | D | D | D | ✕ |
Cortex-M0+ | D | D | D | ✕ |
Cortex-M1 | D | D | D | ✕ |
SC000 (M0 secure) | D | D | D | ✕ |
Cortex-M3 | DT | DT | DT | ✕ |
Cortex-M4 | DT | DT | DT | ✕ |
Cortex-M7 | DT | DT | DT | ✕ |
Cortex-M23 | DT | DT | DT | ✕ |
Cortex-M33 | DT | DT | DT | ✕ |
Cortex-M52 | DT | DT | DT | ✕ |
Cortex-M55 | DT | DT | DT | ✕ |
Cortex-M85 | DT | DT | DT | ✕ |
SC300 (M3 secure) | DT | DT | DT | ✕ |
| Arm Cortex-R | ||||
Cortex-R4 | DT | DT | ✕ | ✕ |
Cortex-R5 | DT | DT | ✕ | ✕ |
Cortex-R8 | DT | DT | ✕ | ✕ |
Cortex-R52 | DT | DT | ✕ | ✕ |
| Arm legacy | ||||
ARM7 | D | ✕ | ✕ | ✕ |
ARM9 | D | ✕ | ✕ | ✕ |
ARM11 | D | ✕ | ✕ | ✕ |
| Cadence | ||||
HiFi 1 | D | ✕ | ✕ | ✕ |
HiFi 3 | D | ✕ | ✕ | ✕ |
HiFi 3z | D | ✕ | ✕ | ✕ |
HiFi 4 | D | ✕ | ✕ | ✕ |
HiFi 5 | D | ✕ | ✕ | ✕ |
Fusion F1 | D | ✕ | ✕ | ✕ |
Xtensa LX6 | D | ✕ | ✕ | ✕ |
Xtensa LX7 | D | ✕ | ✕ | ✕ |
| Microchip | ||||
PIC32MX | D | ✕ | ✕ | ✕ |
PIC32MZ | D | ✕ | ✕ | ✕ |
| Renesas RX | ||||
RX110–RX660 (16 devices) | D | ✕ | ✕ | ✕ |
| RISC-V | ||||
E20 | DT | ✕ | ✕ | DT |
E21 | DT | ✕ | ✕ | DT |
E24 | DT | ✕ | ✕ | DT |
E31 | DT | ✕ | ✕ | DT |
E34 | DT | ✕ | ✕ | DT |
E61 | DT | ✕ | ✕ | DT |
E61-MC | DT | ✕ | ✕ | DT |
E76 | DT | ✕ | ✕ | DT |
E76-MC | DT | ✕ | ✕ | DT |
| SiLabs | ||||
EFM8 | D | ✕ | ✕ | ✕ |
D Debug supported (execution control, memory access, etc.) T Pin trace supported ✕ Not supported Source: extracted automatically from SEGGER's official PDF
J-Link or J-Trace — which to choose
Make this decision at the board-design stage. ETM trace requires trace-port wiring and a connector on the target board (MIPI-60, Mictor 38, etc.). If you decide after the board is finished that you want to chase a bug that will not reproduce, the trace physically cannot be captured without the wiring. Buying another probe does not solve this kind of problem.
J-Link
Normal debugging and programming
- Breakpoints, stepping, and memory inspection are enough
- RTT / SWO is enough for logging
- ETB / MTB (a limited recent window) is enough for trace
- Flash programming or production programming is the main purpose
- The board has no trace-port wiring (or the design cannot be changed)
J-Trace
You need continuous instruction trace
- You want to chase bugs that rarely reproduce (execution history just before a hard fault)
- You need code coverage (regulation, functional safety)
- Performance profiling (Live Code Profiling)
- Analysis of interrupt contention and timing-dependent failures
- The target is Cortex-M3 or later / Cortex-A / R / RISC-V with ETM implemented
J-Trace is a superset of J-Link. It includes J-Link-equivalent debug functions and the advanced-feature licenses (J-Flash, Unlimited Flash Breakpoints, Ozone, etc.), so if you choose J-Trace you normally do not need a separate J-Link.
How to read the tables / notes
[1]These tables cover the current hardware version of each model. On older hardware versions some of the functions listed may not be available. Take care when reusing second-hand or long-stored units.
[2]All speeds are peak values; measured values are lower. They depend on the debug interface and speed selected, the CPU core frequency, other devices on the JTAG chain, and so on. Target flash write speed is often the bottleneck, so on small MCUs with slow flash the difference between PRO and PLUS is hard to notice.
[3]“Unlimited” High Speed Sampling means only the debug interface bandwidth limits it. The typical sampling frequency per variable exceeds 10 kHz.
[4]1 kHz is the guaranteed value for one variable at a suitable target interface speed (at least 1 MHz). Sampling several variables in parallel lowers the maximum frequency.
[5]D = debug supported (execution control, memory access, etc.) / T = pin trace supported. The J-Trace core table is real data extracted automatically from SEGGER's official PDF. The trace-encoder rows are derived from the T marks in the core table.
The figures and support status on this page are taken from SEGGER's official comparison tables (J-Link / J-Trace). Prices change, so they are not listed. For a quote with part numbers and quantities, please contact us.
SEGGER debug probes
Configuration advice and quotes
We can help you choose SEGGER product configurations and licenses. Tell us the following four things and we will propose the complete set of part numbers you need.
- Target MCU / SoC part number
- Debug connector type (the relevant part of the schematic)
- IDE / compiler used
- Quantity and purpose (development / production / CI / integration into your own application)